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DATA DATA PRELIMINARY SHEET SHEET
BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT
PB1005K
REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz RF/IF FREQUENCY DOWN-CONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER
DESCRIPTION
The PB1005K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip. The PB1005K features 36-pin plastic QFN, fixed prescaler and supply voltage. The 36-pin plastic QFN package is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter data. Supply voltage is 3 V. Thus, the PB1005K can make RF block fewer components and lower power consumption. This IC is manufactured using NEC's 20 GHz fT NESATTMIII silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC realizes excellent performance, uniformity and reliability.
FEATURES
* Double conversion * Integrated RF block : fREFin = 16.368 MHz, f2ndIFout = 4.092 MHz : RF/IF frequency down-converter + PLL frequency synthesizer
* High-density surface mountable : 36-pin plastic QFN (6.0 x 6.0 x 0.95 mm) * Needless to input counter data : fixed division internal prescaler * VCO side division * Reference division * Supply voltage * Low current consumption * Gain adjustable externally : / 200 (/ 25, / 8 serial prescaler) : /2 : VCC = 2.7 to 3.3 V : ICC = 45.0 mA TYP.@VCC = 3.0 V : Gain control voltage pin (control voltage up vs. gain down)
APPLICATION
* Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz
ORDERING INFORMATION
Part Number Package 36-pin plastic QFN Supplying Form Embossed tape 12 mm wide. Pin 1 is in pull-out direction. Qty 2.5 kp/reel.
PB1005K-E1
Remark
To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: PB1005K) Caution Electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. P14016EJ1V0DS00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan
(c)
1999
PB1005K
PIN CONNECTION AND INTERNAL BLOCK DIAGRAM
VCC (reference block)
19 18 N.C. 17 REFin 16 N.C. GND 15 (divider block) 14 LOout VCC 13 (divider block) GND 12 (Phase detector) 11 PD-Vout1 10 PD-Vout2 1 2 3 4 5 6 7 8 9
GND (2ndIF-AMP)
2ndIFbypass
VCC (2ndIF-AMP)
2ndIFin1
2ndIFout
2ndIFin2
N.C.
21
27 IF-MIXout 28 N.C. 29 VGC (IF-MIX) 30 VCC (IF-MIX) 31 N.C. 32 IF-MIXin 33 GND 34 (IF-MIX) RF-MIXout 35 VCC 36 (RF-MIX)
26
25
24
23
22
20
/2 /8 /25
PD
1stLO-OSC1
VCC (phase detector)
GND (1stLO-OSC)
RF-MIXin
GND (RF-MIXin)
VCC (1stLO-OSC)
N.C.
REFout
2
Preliminary Data Sheet P14016EJ1V0DS00
1stLO-OSC2
PD-Vout3
PB1005K
PRODUCT LINE-UP (TA = +25 C, VCC = 3.0 V)
Functions (Frequency unit: MHz) VCC (V) ICC (mA) 6.0 CG (dB) 14
Type General Purpose Wideband Separate IC
Part Number
Package 6-pin minimold 6-pin super minimold
Status Available
PC2756T PC2756TB PC2753GR
RF down-converter with osc. Tr 2.7 to 3.3
IF down-converter with gain control amplifier RF/IF down-converter + PLL synthesizer REF = 18.414 1stIF = 28.644/2ndIF = 1.023 RF/IF down-converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092
2.7 to 3.3
6.5
60 to 79 20-pin plastic SSOP (225 mil) 72 to 92 30-pin plastic SSOP (300 mil) Discontinued
Clock PB1003GS Frequency Specific 1 chip IC
2.7 to 3.3
37.5
PB1004GS PB1005GS PB1005K
2.7 to 3.3 2.7 to 3.3
37.5 45.0
72 to 92 72 to 92 36-pin plastic QFN Available
Notice
Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. To know the associated products, please refer to their latest data sheets.
SYSTEM APPLICATION EXAMPLE
GPS receiver RF block diagram
* f0 = 1.023 MHz in the diagram. 60f0 RF-MIXout LNA 1540f0 1540f0 BPF 64f0 8f0 1/25 1600f0 OSC LOOP 8f0 AMP 1stLO-OSC1 1stLO-OSC2 LOOUT VCC TCXO 16.368 MHz 16f0 1/8 PD 1/2 16f0 16.368 MHz Buff to Demodulator RF-MIX BPF IF-MIXin IF-MIX IF-MIXout VGC 40f0 LPF 2ndlFin1 2ndlFin2 2ndlFbypass 2ndlF-Amp 4f0 4.092 MHz Buff to Demodulator * PB1005K is in .
1575.42 MHz from Antenna
e.g. PC2749TB
REF
Caution
This diagram schematically shows only the PB1005K's internal functions on the system. This diagram does not present the actual application circuits.
Preliminary Data Sheet P14016EJ1V0DS00
3
PB1005K
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Total Circuit Current Power Dissipation Symbol VCC ICC PD TA = +25 C TA = +25 C Mounted on double-sided copper clad 50 x 50 x 1.6 mm epoxy glass PWB (TA = +85 C) Conditions Rating 3.6 120 430 -40 to +85 -55 to +150 Unit V mA mW C C
Operating Ambient Temperature Storage Temperature
TA Tstg
RECOMMENDED OPERATING RANGE
Parameter Supply Voltage Operating Ambient Temperature RF Input Frequency 1st LO Oscillating Frequency 1st IF Input Frequency 2nd LO Input Frequency 2nd IF Input/output Frequency Symbol VCC TA fRFin f1stLOin f1stIFin f2ndLOin f2ndIFin f2ndIFout fREFin fREFout fLOout MIN. 2.7 -40 1616.80 TYP. 3.0 +25 1575.42 1636.80 61.38 65.472 4.092 MAX. 3.3 +85 1656.80 Unit V C MHz MHz MHz MHz MHz
Reference Input/output Frequency
16.368
MHz
LO Output Frequency
8.184
MHz
4
Preliminary Data Sheet P14016EJ1V0DS00
PB1005K
ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 C, VCC = 3.0 V)
Parameter Total Circuit Current Symbol ICCtotal Conditions ICC1 + ICC2 + ICC3 + ICC4 MIN. 32.0 TYP. 45.0 MAX. 60.0 Unit mA
RF Down-converter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = -10 dBm, ZS = ZL = 50 ) Circuit Current 1 RF Conversion Gain RF-SSB Noise Figure Maximum IF Output ICC1 CGRF NFRF PO(sat)RF No Signals PRFin = -40 dBm PRFin = -40 dBm PRFin = -10 dBm 6.0 12.5 7.0 -5.5 10.0 15.5 10.0 -2.5 14.0 18.5 13.0 +0.5 mA dB dB dBm
IF Down-converter Block (f1stIFIn = 61.38 MHz, f2ndLOIn = 65.472 MHz, ZS = 50 , ZL = 2 k) Circuit Current 2 IF Conversion Voltage Gain IF-SSB Noise Figure Maximum 2ndIF Output Gain Control Voltage Gain Control Range ICC2 CG(GV)IF NFIF PO(sat)IF VGC DGC No Signals at Maximum Gain, P1stIFin = -50 dBm at Maximum Gain, P1stIFin = -50 dBm at Maximum Gain, P1stIFin = -20 dBm Voltage at Maximum Gain CGIF P1stIFin = -50 dBm 3.4 38 8.5 -9.5 20 5.3 41 11.5 -6.5 7.2 44 14.5 -3.5 1.0 mA dB dB dBm V dB
2nd IF Amplifier (f2ndIF = 4.092 MHz, ZS = 50 , ZL = 2 k) Circuit Current 3 Voltage Gain Output Power PLL Synthesizer Block Circuit Current 4 Phase Comparing Frequency Reference Input Minimum Level Loop Filter Output Level (H) Loop Filter Output Level (L) Reference Output Swing ICC4 fPD PLL All Block Operating PLL Loop
Note
ICC3 GV P2ndIFout
No Signals P2ndIFin = -60 dBm P2ndIFin = -30 dBm
1.55 37 -14.5
2.40 40 -11.5
3.25 43 -8.5
mA dB dBm
18.5 8.0
28.5 8.184
38.5 8.4 0.4
mA MHz
VREFin
ZL = 10 k//20 pF
200
mVP-P
VLP(H) VLP(L) VREFout ZL = 10 k//2 pF
Note
2.8 1.0
V V VP-P
Note Impedance of measurement equipment
Preliminary Data Sheet P14016EJ1V0DS00
5
PB1005K
STANDARD CHARACTERISTICS (Unless otherwise specified TA = +25 C, VCC = 3.0 V)
Parameter Symbol Conditions Reference Unit
RF Down-converter Block (P1stLOin = -10 dBm, ZS = ZL = 50 ) LO Leakage to IF Pin LO Leakage to RF Pin Input 3rd Order Intercept Point LOif LOrf IIP3RF f1stLOin = 1 636.80 MHz f1stLOin = 1 636.80 MHz fRFin1 = 1 600 MHz, fRFin2 = 1605 MHz f1stLOin = 1 660 MHz -30 -30 -13 dBm dBm dBm
IF Down-converter Block (1st LO oscillating, ZS = 50 , ZL = 2 k) LO Leakage to 2nd IF LO Leakage to 1st IF Input 3rd Order Intercept Point VCO Block Phase Noise C/N PLL Loop, 1kHz of VCO wave -78 dBc/Hz LO2ndif LO1stif IIP3IF f2ndLOin = 65.472 MHz f2ndLOin = 65.472 MHz f1stIFin1 = 61.38 MHz, f1stIFIn2 = 61.48 MHz f2ndLOin = 65.472 MHz -20 -40 -34 dBm dBm dBm
6
Preliminary Data Sheet P14016EJ1V0DS00
PB1005K
PIN EXPLANATION
Applied Voltage (V) Pin Voltage (V) 1.68
Pin No. 35
Pin Name
Function and Application
Internal Equivalent Circuit
RX-MIXout
Output pin of RF mixer. 1st IF filter must be inserted between pin 33 & 35. Supply voltage pin of RF mixer block. This pin must be decoupled with capacitor (example: 1 000 pF). Input pin of RF mixer. 1 575.42 MHz band pass filter can be inserted between pin 1 and external LNA. Ground pin RF mixer. Supply voltage pin of differential amplifier for 1st LO oscillator circuit. Pin 4 & 5 are each base pin of differential amplifier for 1st LO oscillator. These pins should be equipped with LC and varactor to oscillate on 1 636.80 MHz as VCO. Ground pin of differential amplifier for 1st LO oscillator circuit. Supply voltage pin of phase detector and active loop filter. Non connection Pins of active loop filter for tuning voltage output. The active transistors configured with darlington pair are built on chip. Pin 11 should be pulled down with external resistor. Pin 9 to 10 should be equipped with external RC in order to adjust dumping factor and cutoff frequency. This tuning voltage output must be connected to varactor diode of 1st LO-OSC. Ground pin of phase detector + active loop filter.
36
36
VCC (RF-MIX)
2.7 to 3.3
1stLO -OSC
35
1
1
RF-MIXin
1.20
2
2 3
GND (RF-MIX) VCC (1stLO-OSC)
0 2.7 to 3.3

3
VCC RF-MIX or Prescaler input
4
1stLO-OSC1
1.88
5
1stLO-OSC2
1.88
4 6
5
6
GND (1stLO-OSC)
0
7
VCC (phase detector)
2.7 to 3.3
8 9
N.C. PD-Vout3
Pull-up with resistor

7
10
PD-Vout2
Output in accordance with phase difference
10 PD 9
11
PD-Vout1
Pull-up with resistor
12
11
12
GND (phase detector)
0
Preliminary Data Sheet P14016EJ1V0DS00
7
PB1005K
Applied Voltage (V) 2.7 to 3.3 Pin Voltage (V)
Pin No. 13
Pin Name
Function and Application
Internal Equivalent Circuit
VCC (divider block) LOout
Supply voltage pin of prescalers. Monitor pin of comparison frequency at phase detector. Ground pin of prescalers + LOout amplifier Non connection Input pin of reference frequency. This pin should be equipped with external 16.368 MHz oscillator (example: TCXO). Non connection Supply voltage pin of input/output amplifiers in reference block. Output pin of reference frequency. The frequency from pin 17 can be took out as 1 VP-P swing. Non connection Output pin of 2nd IF amplifier. This pin output 4.092 MHz clipped sinewave. This pin should be equipped with external inverter to adjust level to next stage on user's system. Supply voltage pin of 2nd IF amplifier. Bypass pin of 2nd IF amplifier input 1. This pin should be grounded through capacitor. Pin of 2nd IF amplifier input 2. This pin should be grounded through capacitor. Pin of 2nd IF amplifier input 1. 2nd IF filter can be inserted between pin 26 & 28. Ground pin of 2nd IF amplifier.
13 1st LO OSC 15
IF MIX /25 /8
PD
14
2.08 1.96
PD 14
/2 Ref.
15
GND (divider block) N.C. REFin
0
16 17
19
18 19
N.C. VCC (reference block) REFout
2.7 to 3.3

20 17 PD
20
1.65
15
21 22
N.C. 2ndIFout

1.56
23 24 22
23
VCC (2ndIF-AMP) 2ndIF bypass
2.7 to 3.3
26
24
2.30
25
25
2ndIFin2
2.35
27
26
2ndIFin1
2.35
27
GND (2ndIF-AMP)
0
8
Preliminary Data Sheet P14016EJ1V0DS00
PB1005K
Applied Voltage (V) Pin Voltage (V) 1.15
Pin No. 28
Pin Name
Function and Application
Internal Equivalent Circuit
IF-MIXout
Output pin from IF mixer. IF mixer output signal goes through gain control amplifier before this emitter follower output port. Non connection Gain control voltage pin of IF mixer output amplifier. This voltage performs forward control (VGC up Gain down). Supply voltage pin of IF mixer, gain control amplifier and emitter follower transistor. Non connection Input pin of IF mixer. Ground pin of IF mixer.
30 31 33 2nd LO 34 28
29 30
N.C. VGC (IF-MIX)
0 to 3.3

31
VCC (IF-MIX)
2.7 to 3.3
32 33 34
N.C. IF-MIXin GND (IF-MIX)
0
2.00
Caution
Ground pattern on the board must be formed as wide as possible to minimize ground impedance.
Preliminary Data Sheet P14016EJ1V0DS00
9
PB1005K
TEST CIRCUIT
50 Signal Generator C20 27 Spectrum Analyzer R6 C21 28 29 C22 30 31 32 50 Signal Generator Spectrum Analyzer VCC C3 C1 33 34 35 C2 36 1 50 Signal Generator VCC C5 R1 L R2 C9 C4 2 3 C6 V-Di 4 5 6 C7 C8 7 8 R3 VCC 9 C10 R4 10 18 17 50 C13 Signal Generator C19 26 25 24 Spectrum Analyzer C17 C18 23 R5 C16 C15 22 21 20 19 Osilloscope VCC C14
VCC
To get maximum gain. Apply 1.0V MAX.
/2 /8 /25
PD
16 15 14 C12 13 C11 12 11
VCC
C23
Osilloscope VCC
Spectrum Analyzer : measure frequency Oscilloscope : measure output voltage swing
Component List
Form Chip capacitor Symbol C1 to C5, C8, C11 to C15, C17, C18, C22 C6, C7 C9 C10 C19 C23 C16, C20 C21 Chip resistor R1, R2 R3 R4 R5, R6 Varactor Diode Chip Inductor V-Di L Value 1 000 pF 24 pF (UJ) 1800 pF 33 nF 10 000 pF 1 F 0.1 F 0.01 F 4.7 k 6.2 k 1.2 k 1.95 k 1SV285 3.9 nH
10
Preliminary Data Sheet P14016EJ1V0DS00
PB1005K
PACKAGE DIMENSIONS
36 PIN PLASTIC QFN (UNIT: mm)
6.20.2 4-C0.5 6.00.2
6.00.2
6.20.2
6.20.2
Pin36
Pin1
6.00.2
0.220.05
0.60.1
6.20.2 6.00.2
1.0MAX
0.50.025
Bottom View
Preliminary Data Sheet P14016EJ1V0DS00
11
PB1005K
NOTE ON CORRECT USE
(1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor (example: 1 000 pF) to the VCC pin. (5) Frequency signal input/output pins must be each coupled with external capacitor for DC cut.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Soldering Method Infrared Reflow Soldering Conditions Package peak temperature: 235 C or below Time: 30 seconds or less (at 210 C) Note Count: 2, Exposure limit : None Pin temperature: 300 C Time: 3 seconds or less (per side of device) Note Exposure limit : None Recommended Condition Symbol IR35-00-2
Partial Heating
-
Note After opening the dry pack, keep it in a place below 25 C and 65 % RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
12
Preliminary Data Sheet P14016EJ1V0DS00
PB1005K
[MEMO]
Preliminary Data Sheet P14016EJ1V0DS00
13
PB1005K
[MEMO]
14
Preliminary Data Sheet P14016EJ1V0DS00
PB1005K
[MEMO]
Preliminary Data Sheet P14016EJ1V0DS00
15
PB1005K
ATTENTION
OBSERVE PRECAUTIONS FOR HANDLING
ELECTROSTATIC SENSITIVE DEVICES
NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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